Bolt Graphics tapes out its first Zeus GPU test chip on TSMC 12nm — firm touts 17x lower cost of compute

Bolt Graphics has announced its completed tape-out of a test chip for its Zeus GPU, marking the California-based startup’s first move from FPGA emulation to manufactured silicon — which it claims can deliver 17 times lower cost of compute.

The test chip was designed into TSMC’s 12nm FFC process and will be used for customer benchmarking ahead of a planned production ramp in Q4 2027. Bolt says it’s targeting companies in the HPC, electromagnetic simulation, and graphics rendering markets, which it values at over $55 billion combined, that “can’t afford the level of compute needed for their applications.”

This is a concrete step for a company whose ambitious performance claims have, until now, rested entirely on internal simulations and FPGA testing. When Bolt first introduced Zeus in early 2025, it said the GPU could deliver up to 10 times the path tracing throughput of Nvidia’s GeForce RTX 5090. Those figures obviously drew attention as well as skepticism, given the absence of working silicon. In a set of FAQs released alongside the announcement, Bolt says that its architecture has been running on FPGA and under evaluation by customers for four years.

TSMC’s 12nm FFC node is part of the company’s mature 16nm/12nm FinFET family, offering lower cost and well-established IP libraries compared to leading-edge processes. According to Bolt, however, the Zeus architecture is also designed for “advanced nodes, including 5nm,” suggesting the 12nm test chip is more of a validation step and that the company will look to use more advanced nodes for final production.

According to Bolt’s product specs, Zeus will ship in PCIe card and 2U server form factors. The PCIe cards range from a single-slot, 120 W model with 5/10/20 TFLOPS at FP64/FP32/FP16, up to a dual-slot, 250 W card offering twice those figures. All cards feature 128 MB to 256 MB of on-chip cache, up to 384 GB of memory through a combination of soldered LPDDR5X and DDR5 SO-DIMMs, and integrated 400 GbE networking.

Bolt’s stated product pipeline exceeds $500 million, and the company says over 14,000 enterprises, developers, and end users have joined its early access program. It closed a Series A that was reportedly 50% oversubscribed, though neither the funding amount nor lead investors have been disclosed.

Timelines have shifted somewhat since Bolt first appeared on the scene, with the company originally aiming for developer kits in late 2025 and production in late 2026. At CES in January, the company demoed a prototype card but still lacked functional silicon. This new announcement pins production to Q4 2027 to supply chains for HPC, rendering, and next-gen workloads, with no updated timeline for developer hardware.

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